This invention relates to semiconductor devices and methods of manufacture, and more particularly to an improved method for making source/drain diffusions in the manufacture of read/write memory devices or the like, using N-channel silicon gate processing.
Semiconductor devices such as read/write memory arrays are commonly made by single-level or double-level polysilicon N-channel self-aligned processes such as shown, for example, in U.S. Pat. Nos. 4,055,444 and 4,388,121, issued to G. R. Mohan Rao, assigned to Texas Instruments.
In the processes used for these prior dynamic RAM cell arrays, the bit lines and source/drain regions were usually formed by an N+ arsenic implant. The implant was performed after the polysilicon (used as a self-aligning mask and as the MOS transistor gate) had been patterned.
The arsenic implant (or phosphorus predeposition) and its associated process steps, such as a thermal oxidation, add complexity to the manufacturing sequence, and, just as from any other process steps, contribute to defect densities and thereby reduce the yield. As set forth in pending application Ser. No. 156,533 entitled "Shielding for Implant in Manufacture of Dynamic Memory" filed, June 5, 1980, assigned to Texas Instruments, the arsenic implant can cause a build-up of charge on the transistor gates, resulting in thin oxide failures.
Phosphosilicate glass is used in fabrication of MOS devices for electrical isolation between the top layer metallization and underlying polysilicon. This material acts as a barrier against diffusion of mobile ions, improving the stability of the device. The glass is reflowed after contact holes have been etched, providing a smooth contour and improving integrity of the step coverage for the metal interconnects.
It is the principal object of this invention to provide an improved method of making semiconductor dynamic read/write memory devices or the like. Another object is to provide a simplified method of making memory cell arrays or other semiconductor devices of small cell size, yet by a process compatible with standard N-channel processing.